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6 Yrs
B-712, Sigma 2 Office Bldg, Gumi-Dong 18, Bundang-Gu, Sungnam-Si, Kyunggi-Do
Anyang, Gyeonggi-Do-463741, Korea+(82)-31-6053800
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Fully Integrated Mixed-Signal System

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▣ High-performance, Low-power 32bit Microcontroller
▣ Advanced EISC Architecture
- 48Mhz speed
- 3 Stage Pipeline
- General Registers : 32 Bit * 8
- Special Registers : 32 Bit * 6
16 Bi I i S A hi
▣ Analog Peripherals
- Three OP amp
Gain 80db, SNR under 10nV
- Three Comparator
- 6ch 10 bit ADC with a Sampling rate of 200k bps
- Bit Instruction Set Architecture
- On-Chip Debugger (On Silicon ICE)
- Efficient in C compiler
- Efficient conditional instruction
- Extendable Instruction Set (LERI)
- 1cycle multiplier
- lower power and high performance
▣ Special Microcontroller Features
Power Dissipation under 1.9mW
Dynamic Performance ENOB 9.8, SFDR 65.9dB
SIND 61.2dB
Linearity INL under 2 LSB
DNL under 1 LSB
Internal Voltage Reference
- Voltage Regulator
3.3V – 5.0V (10mA)
- Power on Reset
- Power saving management
- Software selectable clock frequency


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