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The eos (adc32A312) 32bit EISC micro controller is designed to provided a cost-effective and high
performance micro controller solution for EFT/POS & Pinpad appliance and general application. The eos is built
around an outstanding CPU core with 5 stage pipeline: the 32bit Advanced EISC processor designed by ADC.
To reduce total system cost, the eos offers Harvard cache with MMU. Important functions include Nand Flash
Memory Controller,4ch. UART, Key scan, 10bit ADC and SRAM for boot loader.
Features
Built in 32bit CPU, Cache and MMU (TLB)
- Maximum 50Mhz CPU Operation
- High Performance EISC Core AE32000
- 2 Way Set Associative Harvard Cache with 2Kbyte Instruction
and 2Kbyte Data Cache
- Pseudo LRU (Least Recently Used) Replace Algorithm
- Write Through / Write Back Policy to maintain the coherence
between main memory and cache memory
- Write Buffer with 4 Depths
- Support 64 entry, 4 way set associative MMU
- Support Correcting misalignment by hardware
- Support Little / Big Endian
Memory Management
- 32MByte Address Space per each bank
- Support 8 Memory banks and another memory bank
for Debugging
- Supports External Wait Signal to Expand the bus cycle
- Supports Self-refresh mode in SRAM / SDRAM for Power down
- Supports Asymmetric / Symmetric Address of DRAM
􀀖 Clock Power Management
- On-chip PLL makes the clock for operating MCU
- Clock can be fed selectively to each function block by software
- Support Power Down Mode
- Normal mode: Normal operation mode
- Slow mode: Low frequency clock without PLL

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