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DDR Termination Regulator

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FEATURES
- Low Output Voltage Offset
- Works with +5V, +3.3V, and 2.5V Rails
- Source and Sink Current
- Low External Component Count
- No External Resistors Required
- Linear Topology
- Available in SOP8, SOP8-PP Package
- Low Cost and Easy to Use

TJ2995

SOP8 & SOP8PP
DESCRIPTION
The TJ2995 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transient. This device can deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. With an independent VSENSE pin, the TJ2995 can provide superior load regulation. The TJ2995 provides a VREF output as the reference for the chipset and DDR DIMMS. The TJ2995 can easily provide the accurate VTT and VREF voltages without external resistors that PCB areas can be reduced. The quiescent current is low to meet the low power consumption applications.

Ddr Termination Regulator

FOB Price : Get Price

FEATURES
- Source and sink current
- Low output voltage offset
- No external resistors required
- Linear topology
- Suspend to Ram (STR) functionality
- Low external component count
- Thermal Shutdown
- Available in SOP8, SOP8-PP Packages
TJ2996
SOP8 & SOP8PP
DESCRIPTION
The TJ2996 linear regulator is designed to meet the JEDEC SSTL-2 and SSTL-3 specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transient. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The TJ2996 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. An additional feature found on the TJ2996 is an active low shutdown pin that provides Suspend To RAM (STR) functionality. When is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

Ddr Termination Regulator

FOB Price : Get Price

Features
- source and sink current
- low output voltage offset
- no external resistors required
- linear topology
- suspend to ram (str) functionality
- low external component count
- thermal shutdown
- available in sop8, sop8-pp packages
Tj2997
Sop8 & sop8pp
Description
The tj2997 linear regulator is designed to meet the jedec sstl specifications for termination of ddr-sdram. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering up to 1.5a continuous current and transient peaks up to 3a with respect to pvin operating condition in the application as required for ddr-sdram termination. The tj2997 also incorporates a vsense pin to provide superior load regulation and a vref output as a reference for the chipset and dimms. An additional feature found on the tj2997 is an active high enable (en) pin that provides suspend to ram (str) functionality. When en is pulled low the vtt output will tri-state providing a high impedance output, but, vref will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

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